A arithmetic processing device (processor, central processing unit (CPU)) has a cache memory to avoid a long latency for accessing a main storage unit (main memory) provided outside. The cache memory stores data read out from the main memory when the processor executes a memory access command (or instruction). Then, when executing the memory access command again about the same address, the processor reads out the data from the cache memory to avoid accessing the main memory.
When the command issuance unit of the processor issues the memory access command (or request), the memory access request is input to a cache. Then, the cache executes a cache determination as to whether data on an access address has been retained by the cache memory. When it is determined that a cache hit occurs, the cache returns the data in the cache memory (returns a response with data) to the command issuance unit. On the other hand, when it is determined that a cache miss occurs, the cache issues a move-in request to a low-level cache closer to the main memory or a memory control circuit.
The move-in request is a request for which a certain-level cache requests a low-level cache closer to the main memory or the memory control unit to give data on an access address, therefore, the move-in buffer is a type of a memory access request. The move-in request is issued by a cache in which a cache miss has occurred.
The move-in request is described in Japanese Laid-open Patent Publication Nos. H08-328960 and H09-218823.
Since it may take a long time from the issuance of a move-in request to a data response, a move-in buffer capable of having registered therein information indicating that the move-in request has been issued is provided, for example, between an L1 cache and an L2 cache (or between the L2 cache and an L3 cache). When issuing the move-in request, the L1 cache acquires the move-in buffer and registers, in the move-in buffer, information on the move-in request, i.e., index information (index address) on a cache memory in which a cache miss has occurred and way information on the cache in which response data is to be registered after a data response.
After the L2 cache issues an ejection request to eject old data that has been registered in the L1 cache to the L1 cache and the data is ejected from the L1 cache to the L2 cache, the L1 cache receives data from the L2 cache and stores the new data in the data region of the corresponding move-in buffer. Then, the L1 cache registers the new data in an L1 cache memory based on the index information and the way information that have been registered in the move-in buffer, and returns the data to the command issuance unit (or an upper level cache more distant from the main memory). After giving the data, the move-in buffer that has acquired the information on the move-in request is opened. By registering information of a plurality of move-in requests registered in the move-in buffer, the L1 cache issues a next move-in request before receiving a data response for a preceding move-in request.